The present invention relates to handling processor interrupts, and more specifically, to handling interrupts within a hierarchical interrupt register structure.
In computing systems, interrupts are used to alert a processor to an event that has occurred within the system that requires immediate attention. Interrupts generally cause the processor to halt the execution of the current thread, save data related to its current state, and execute an interrupt handler to address the event that caused the interrupt. Once the interrupt handler has completed its routine, the processor resumes execution of the thread using its saved state data.
Naturally, speed of execution is an important concern for system interrupt handlers, as the time spent by a system interrupt handler to handle various interrupts directly reduces the amount of time and processing resources that would otherwise be available to execute computing threads. Thus, numerous interrupts, or even a few interrupts that require long-running recovery actions, can drastically reduce the performance and functionality of the system through excessive amounts of processing time spent handling those interrupts.